Design of Parallel Adder

Parallel adder is a combinational circuit, used to add multi-bit binary numbers. With half adder and full adder in use, What is the need for going to parallel adder? What is parallel adder? How it works?

In this topic, you will get answer for all the above questions.

What is the need for parallel adder?

Half adder is used to add only two single bit binary digits(A and B). Using full adder, addition of two single bit binary digits(A and B) along with the carry from the previous digit addition is possible.

But, if we have to add two multi bit binary digits(eg. 1011 and 1001), What to do? Think of the situation given in the below diagram.

The simple solution to add multi bit binary number is the design of parallel adder.

What is Parallel Adder?

Parallel adder is a combinational logic circuit used to add multi bit binary digits. To perform this addition, full adders are cascaded with one another. The number of full adders to be cascaded depends on the number of bits in a binary digit.

For example, if you want to add two 4-bit binary numbers, you have to connect 4 number of full adders in parallel. The below block diagram shows ‘n’ number of full adders cascaded with one another to design a n-bit parallel adder.

As you can see in the diagram, A_n….A₂ A₁ A₀ and B_n….B₂ B₁ B₀ are the n-bit binary digits, which are to be added. The least significant bit(A₀ and B₀) are given as the input for first full adder. The next bits(A₁ and B₁) are given as the input for second full adder. Similarly, the most significant bits(A_n and B_n) of the two binary inputs are given as the input for the last full adder.

How the parallel adder works?

Initially the Carry input(C_i0) for the first full adder is set to 0. The first full adder adds the first two bits(A₀ and B₀) and carry input(C_i0). It will produce the sum output S₀ and carry(C₀). This carry output(C₀) from the first half adder is given as the carry input(C_i1) for the second full adder.

The second full adder adds the next two bits (A₁ and B₁) and the carry input(C_i1) from the first full adder. This will produce the sum output S₁ and carry(C₁). This will be continued till the n^th bits are processed by the n^th full adder.

At the end of this addition process, the sum output is produced by all the full adders, which is equivalent to S_n….S₂ S₁ S₀. C_n is the carry bit produced at the end of the addition process.

Design of 3-bit parallel adder

To design a 3- bit parallel adder, 3 full adders have to be considered. Two 3-bit binary numbers(A₂ A₁ A₀ and B₂ B₁ B₀) are considered as input. The parallel adder will produce a 3-bit binary output S₂ S₁ S_0.

Disadvantages

You could observe from the operation of parallel adder, that the carry bit is received by the second full adder, only after the operation of first full adder. Similarly, the nth full adder has to wait for the carry bit to be received from the (n-1)th full adder.

So we could say that, each full adder has to wait for some time to execute until the input carry occurs. This waiting time or delay is called as carry propagation delay.

Since the carry input to a full adder moves from one adder to the next adder, the parallel adder is also called as ripple carry adder.

The delay in execution time due to the carry bits can be increased by using logic gates to eliminate the inter stage carry bits. Such adder is called look ahead carry adder or fast adder.