Design of parallel subtractor

The parallel subtractor is similar to the design of a parallel adder, both in its structure and operation. It is a combinational circuit, used to perform subtraction of multi-bit binary numbers.

Why parallel subtractor?

As you know, half subtractor is used to subtract two single bit digits. Full subtractor is used to subtract a single bit binary number from another single bit binary number with borrow from the previous digit subtraction process.

But if it is a multi-bit binary number, either half subtractor or full subtractor cannot perform the subtraction. We have to look after another logic circuit, which is nothing but a parallel subtractor.

The computation shown above can be performed with the help of parallel subtractor.

What is Parallel subtractor?

A parallel subtractor is a combinational logic circuit used to subtract two multi-bit binary numbers. To perform this computation, we can use either full adders or full subtractors to build the logic circuit.

To do so, full adders or full subtractors are cascaded with one another. The cascading depends on the number of bits in the binary input. For example, if you have to subtract two 4-bit binary digit, then we have to connect 4 number of full adders or full subtractors in parallel.

Method 1 – Design using full adder

In general, binary subtraction can be performed either by 1’s complement or 2’s complement. Binary subtraction of two binary numbers(A-B) using 2’s complement is done by taking 2’s complement of B and adding it to A. Here, 2′ complement can be obtained by taking 1’s complement and adding ‘1’ to the least significant bit.

To design a logic circuit for a parallel subtractor, let us consider the parallel adder circuit. In this, 2’s complement of B can be implemented by two steps

• First, Invert the B input(by inserting a NOT gate for all the B inputs) to get 1’s complement.
• Then add ‘1’ to the least significant bit through the carry input(C_i0) pin to the first adder to get 2’s complement.

Thus the full adder here performs the subtraction operation for parallel subtractor.

As you can observe from the diagram, there are n-bit binary inputs, A_n….A₂ A₁ A₀ and B_n….B₂ B₁ B₀, where A_n….A₂ A₁ A₀ is the minuend bits and B_n….B₂ B₁ B₀ are the subtrahend bits.

The least significant bit(A₀ and B₀) are given as the input for the first full adder. The next bits(A1 and B1) are given as the input for the second full adder. Similarly, the most significant bits(A_n and B_n) of the two binary inputs are given as the input for the last full adder.

The minuend bits are given directly to the full adder. The subtrahend bits are inverted or complemented by using a NOT gate and given to the full adder. The carry input for the first full adder is set to ‘1’.

The sum output of each full adder S_n….S₂ S₁ S₀ corresponds to the difference output Dn….D2 D1 D0 of each bit in a multi-bit binary number. If there is any carry produced at the nth block, it will be seen at C_0n.

Method 2 – Design using full subtractor

In this method, the design is very simple and same as that of the parallel adder. Here, the number of full subtractors used depend on the number of bits in the binary input.

As you can observe from the below diagram, the first full subtractor(FSo) subtract the two bits and outputs the difference at D₀. The carry output from FSo is given as the input for the next successive block FS1 to perform its operation. This process continues till it executes all the bits in the binary number.

At the end, you will be getting the difference output as D_n….D₂ D₁ D₀ and carry as C_0n, if any.

Disadvantage

From the working of parallel subtractors, it can be seen that each and every block in the logic circuit executes only when the carry bit is received. So the parallel subtractor has a delay in its execution, called carry propagation delay.