JK flip-flop | Circuit, Truth table and its modifications
JK flip-flop is designed to overcome the invalid or indeterminate state of SR flip-flop. This flip-flop is also a modification of SR flip flop, invented by Jack Kilby, hence the name JK flip flop.
What is JK flip-flop?
JK flip flop is a sequential bi-state single-bit memory element. It has two inputs(J and K), two outputs(Q and Q’) and a clock pulse input. It can be triggered either at the positive edge or at the negative edge of the clock pulse.
The JK flip-flop can be designed from an SR flip flop, by inserting AND gates at the input pins S and R. One input of each AND gate is connected to the output pins Q and Q’. Another input of each AND gate is named as J and K.
The same circuit can be implemented by using NAND gates, adding an extra terminal to the NAND gates A and B.
Now let us look at the operation of JK flip flop.
Operation and truth table
Case 1 : J = K = 0
For this input condition, irrespective of the other inputs for NAND gates A and B, S’ = 1 and R’ = 1. For present state outputs, Q = 1 and Q’ = 0, the next state outputs are Q+1 = 1, Q’+1= 0. There is no change in the output.
For Q = 0 and Q’ = 1, the next state outputs are Q+1 = 0, Q’+1 = 1. Thus there is NO CHANGE in the next state output.
Case 2 : J = 0, K = 1
For this input condition, irrespective of other input for NAND gate A, the output produced is S’ = 1. Let the present state output be Q = 0 and Q’ = 1. The inputs for NAND gate B are K = 1 and Q = 0, which produces R’ = 1.
Now the inputs for NAND gate C are S’ = 1, Q’ = 1 and the next state output produced is Q+1 = 0. For NAND gate D, the inputs are R’ = 1, Q = 0 and the prouced output is Q’+1 = 1.
Thus, for inputs J = 0, K = 1 and present state inputs Q = 0 and Q’ = 1, the obtained next state outputs are Q+1 = 0 and Q’+1 = 1, so there is NO CHANGE is the state of JK flip flop.
Let the present state inputs be Q = 1 and Q’ = 0. For J = 0, K = 1, the output produced by NAND gates A and B are S’ = 1 and R’ = 0. For this SR input value, when you look at the truth table of SR flip flop, the flip flop will RESET its state.
Case 3 : J = 1, K = 0
In this case, the output of NAND gate B is R’ = 1, irrespective of its other input. Now, let us consider the present state be Q = 0 and Q’ = 1. The inputs of NAND gate A are J = 1 and Q’ = 1, the output thus produced is S’ = 0.
For the SR input values, S’ = 0 and R’ = 1, when you look at the truth table of SR Flip lop, the flip flop will SET.
Now, for the present state values Q = 1 and Q’ = 0, the output of NAND gate A and B are S’ = 1 and R’ = 1. For this SR input value (truth table of SR flip flop), the state of the flip flop has NO CHANGE.
Case 4 : J = K = 1
For the present state inputs Q = 0 and Q’ = 1, the NAND gate outputs A and B are S’ = 0 and R’ = 1. From the truth table of SR flip flop, it can be observed that, for S’ = 0 and R’ = 1, the flip flop will SET its state.
Now, for the present state inputs, Q = 1 and Q’ = 0, the gate outputs of A and B are S’ = 1 and R’ = 0. From the truth table of SR flip flop, for the obtained SR inputs, the flip flop will RESET its state.
For J = K = 1, the flip flop continuously changes its state from SET to RESET. It means, the flip flop toggles the flip flop output.
As long as the input is J = K = 1 and for high clock pulse, the flip flop output will toggle. This leads to uncertainty in determining the output Q of the flip flop. This problem is referred to as the race-around condition.
To overcome this problem, a Master-slave configuration of JK flip flop is developed.
Master-slave JK flip flop
It consists of two clocked JK flip flops, connected back to back, as shown in the figure below. One flip flop acts as a master and the other flip flop acts as a slave. The input is given to the master flip flop. The output of master JK flip flop is fed as an input to the slave JK flip flop.
The clock pulse is directly connected to the master flip flop. The inverted pulse is given to the slave flip flop with the help of an inverter. Thus J and K inputs are transmitted to the output of the master flip flop during the positive clock pulse. It is held there until the negative clock pulse occurs. During the negative clock pulse, it is sent to the output of the slave JK flip flop.
How master-slave JK flip flop works?
When J = K = 0, the master output has no change during a positive clock pulse. The master JK flip-flop gets latched during the negative clock pulse. Any input on the master flip flop will be ignored during the negative clock pulse. Thus the slave device will work and its output has also no change in its state.
When J = 0, K = 1, the master flip flop resets during the positive clock pulse. The slave JK flip flop will reset during the negative clock pulse. When J = 1, K = 0, the master will Set during the positive clock pulse. The slave will set during the negative clock pulse.
When J = K = 1, the master will toggle its output during the positive clock pulse. At a negative clock pulse, the master flip flop will stop its work or get latched. The toggled output at the master is copied to the slave during the negative clock pulse.
T flip-flop
T flip flop is a modification of JK flip-flop. The J and K inputs are connected together to get the T input of flip flop. It is also called as Toggle flip flop.
Its operation is very simple. When T = 0, J =K = 0, from the truth table of JK flip flop, it is found that, there is NO CHANGE in the next state. When T = 1, J = K = 1, the output toggles, as it can be observed from the truth table of JK flip flop.
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