Programmable Read-Only Memory(PROM)

Programmable Read-only memory is one of the types of Programmable logic Devices (PLDs). PLDs are integrated circuits that perform a logic function based on user requirements.

In general, a logic gate is an electronic component or integrated circuit that is designed to perform a specific function that is decided at the time of manufacturing the component. The function cannot be changed at a later time.

For example, an AND gate will perform only multiplication operations. It will not perform an addition or inversion operation. Similarly, there are ICs which are which do their fixed-function, and hence they are called fixed-function ICs.

In the case of programmable logic devices, the ICs can be reprogrammed to perform any logic function at any number of times. Depending on the application, any individual user can configure the PLDs.

Since it can be reprogrammed in a few seconds, it gives more flexibility to experiment with designs. The PLDs consist of OR array and AND array. Because of its simple construction, it offers many advantages like low cost, less power consumption, highly reliable and require less time to design.

The Programmable logic devices are classified into PROM, PAL, PLA, CPLD and FPGA. In this article, let us discuss about PROM.

Block diagram of Programmable Read-Only Memory(PROM)

Read-only memory is a basic memory unit of any computer system. As like Random Access Memory(RAM), ROM is a non-volatile memory, where the stored data cannot be erased even when the power is turned off.

PROM is a type of ROM, where the data can be stored and the stored data can be changed by reprogramming the device. This is done either by the PROM programmer or by simply burning the fuses in the PROM.

PROM consists of fixed AND array and programmable OR array. The block diagram of PROM is shown below. It has n inputs and m outputs. For n input variables, there are 2ⁿ distinct addresses. In simple words, we can say that the fixed AND array acts as a decoder(n:2ⁿ).

What is array logic symbol?

In PLDs, number of logic gates are used and they are interconnected with each other through different paths. So in order to simplify the connection between the gate array, the array logic symbol(fixed AND gate array and Programmable OR gate array) is used as shown below.

It uses a single horizontal line connected to the gate input and multiple vertical lines to indicate the individual inputs for that gate. For fixed gate array, dots are placed at the intersection and for programmable gate array, fuses are placed(indicated as ‘x’) at the intersection.

Operation of PROM

The below circuit shows the representation of 4×2 PROM. Here, the two input variables are decoded into 4 lines by means of 4 AND gates and 2 NOT gates. The four outputs of the decoder represent one of the minterms of 2-input variables.

The four outputs are then connected to the OR gates through fuses. Each OR gate has 4 fuses, which depends on the number of decoded outputs from the AND gate.

Depending on the user requirement, the fuses are blown to disconnect particular input(or product term or minterm) for that OR gate. Thus the output of the OR gate(F₁ and F₂) depends on the fuses that are intact with the AND gate output.

Any type of Boolean function or truth table of a combinational circuit can be realize with the help of programmable read-only memory.

Solved example

Now, let us look at an examples.

Let us realize the Boolean function W(a, b, c) = ∑ m(1,3 ,6, 7) and X(a, b, c) = ∑ m(0, 2, 4, 5) using PROM.

The given functions have three input variables(a, b, c) and two outputs(W, X). The three input variables are decoded into 2³ = 8 minterms through 8 AND gates. Since there are two boolean functions in the given problem, two OR gates are used.

For the first OR gate, the fuses for the minterms 1, 3, 6, 7 are intact and the fuses for the other minterms are blown out. For the second Boolean function, the fuses for the minterms 0, 2, 4, 5 are intact, whereas the other fuses are blown out.