Synchronous counter | Types, Circuit, operation and timing Diagram

The synchronous counter is also an application of flip-flop. Each flip-flop used in this counter is synchronized at the same time. That is, the counter is clocked such that, if each flip-flop is triggered at the same time through the clock pulse, then it is called synchronous counter.

To design a synchronous counter, Toggle flip-flop or T flip-flop is used. The clock pulse is given to all the flip-flops in the counter.

In this article, we will discuss the circuit, operation and timing diagram of synchronous up counter, synchronous down counter and synchronous up/down counter. Also, learn the design of synchronous counter.

3-bit synchronous up counter

Synchronous up Counter counts the number of clock pulses at its input from minimum to maximum. A 3-bit counter consists of 3 flip-flops and has 2³ = 8 states from 000 to 111.

The circuit of the 3-bit synchronous up counter is shown below. The clock pulse is given for all the flip-flops.

The T_A input for the first T-flip-flop TFF1 is always maintained at logic HIGH. The output of TFF1 is fed as an input for TFF2. The Q_A and Q_B output of TFF1 and TFF2 are ANDed together and its output is given to the TFF3. The output states of the counter can be observed at Q_CQ_BQ_A.

Operation and Timing Diagram

Before going into the operation of the 3-bit synchronous counter, learn how JK flip-flop and T flip-flop operates.

Let us assume the initial condition as Q_CQ_BQ_A = 000.

The HIGH input is given only to the first flip-flop(TFF 1). Since Q_A = Q_B = 0, the inputs are 0 for the remaining flip-flops. Thus T_A = 1, T_B = 0, T_C = 0.

During the falling edge of the first clock pulse input, the output of TFF 1 toggles and produces Q_A = 1. For the remaining flip flops, there will be no change in the state.

The output becomes Q_CQ_BQ_A = 001. Thus the counter is incremented by 1(000 -> 001).

Now, the input for TFF 1 is T_A = 1. As Q_A becomes 1, the input for TFF 2 becomes T_B = 1. and the input for TFF 3 has no change T_C = 0.

During the negative edge of the second clock pulse, the output of TFF 1 toggles and produce Q_A = 0. At the same time, TFF 2 also toggles and produces Q_B = 1, whereas there will not be a change in the state of TFF3.

Thus the output becomes Q_CQ_BQ_A = 010. So the counter increases its value to 2(001 -> 010).

Now, the input for TFF 1 is T_A = 1. As Q_A and Q_B output are 0 and 1 respectively, the input T_B = 0 and the input will be T_C = 0.

During the negative edge of the third clock pulse, the TFF 1 will toggle to produce Q_A = 1. Since T_B = 0, there will not be any change in the state of TFF 2, so its output will be Q_B = 1. Since T_C = 0, there will not be a change in the output of TFF3, Q_C = 0.

Thus the output now becomes Q_CQ_BQ_A = 011. So the counter increments its value to 3(010 -> 011). Now, the inputs of the flip-flops will become, T_A = 1, T_B = 1, T_C = 1.

During the negative edge of the fourth clock pulse, the output of TFF1 will toggle, so QA = 0, Since T_B and T_C inputs are HIGH, both the flip-flops will toggle its output, so Q_B = 0, Q_C = 1. Now the output becomes Q_CQ_BQ_A = 100 and so the counter value increases to 4(011 -> 100).

The operation continues and counts the clock pulses until it reaches the final state Q_CQ_BQ_A = 111. At the next clock pulse, the counter resets to 000 and starts to count from the first.

4-bit Synchronous up counter

Similar to the 3-bit synchronous up counter, a 4-bit up counter can be designed, but with 4 flip-flops. It is shown in the below diagram. It has 16 output states, that this counter can count from 0000 to 1111.

The timing diagram of the 4-bit synchronous up counter is shown below. The operation is similar to that of a 3-bit counter, which is as explained above.

Synchronous Up/Down counter (or) Bidirectional counter

The synchronous Counter can be made to operate as an up counter and as a down counter with the help of control signals. Since it is capable of counting in either direction, It is also called a bidirectional counter.

In this bidirectional counter, the JK flip-flop is configured as a T flip-flop for storing a bit. The diagram shown below represents the circuit of 3-bit bidirectional counter. Since it is a 3-bit counter, it has 8 possible output states.

Depending on the control input, the counter will count either upward or downward. If the counter counts in an upward direction, it will count from 0 to 7. When the control input is changed, the counter will count in a downward direction from 7 to 0.

The control input decides which direction the counter operates. When control input = 1, it will disable the AND gates 2, 4 and enable gates 1, 3. At this condition, the counter will count upwards.

When the control input is 0, it will enable the AND gates 2, 4 and disable gates 1, 3. uring this condition, the counter will count downwards from 111(7) to 000(0). The timing diagram of the bidirectional counter is shown below.