Emitter Coupled Logic (ECL)

Emitter-coupled logic is the fastest of all digital logic families. It was invented by Hannon S. Yourke in the year 1956 at IBM. It is also called as current mode logic. The design of ECL circuit consists of transistors and resistors.

By preventing the transistor from entering into saturation, the high-speed operation is achieved in ECL logic family. Very small voltage swing is necessary to switch between the two different voltage levels. This cannot be achieved in transistor-transistor logic, as the transistors enter into saturation mode, while in operation.

Emitter-coupled logic family offers an incredible propagation delay of 1ns. The delay is more reduced in the latest ECL families.

In this section, you will learn about the operation of basic emitter-coupled logic implemented for inverter circuits and OR/NOR gate.

Inverter circuit of emitter-coupled logic

The circuit shown below represents the emitter-coupled logic circuit of an inverter. It has two NPN transistors connected in differential single-ended input mode.

Both the emitters are connected together with common resistance R_E. It is a current limiting resistance, used to prevent the transistor from entering into saturation.

It has two outputs: inverting output(V_OUT1) and non-inverting output(V_OUT12). V_IN is the input terminal, where LOW or HIGH input is given.

When the input is HIGH, it will turn ON the transistor Q₁ but not saturated and the transistor Q₂ is turned OFF. This will pull the output V_OUT2 to HIGH but due to the drop in resistant R₁, the output at terminal V_OUT1 will be at LOW value.

On the other side, when the input V_IN is given LOW value, it will turn OFF the transistor Q₁ and the transistor is turned ON. The transistor Q₂ will not enter into saturation.

It will make the output at terminal V_OUT1 to be pulled HIGH value. Due to the drop in resistance R₂, the output at terminal V_OUT2 will have LOW value.

Two input ECL OR/NOR gate

The following circuit is the Emitter-coupled logic circuit of the 2-input OR/NOR gate. It is the slight modification of the inverter circuit given above. In this, an additional transistor is used at the input side.

The operation is simple as explained above. If the input at both the transistors Q₁ and Q₂ are LOW, it will make V_OUT1 to HIGH value. It corresponds to the NOR gate output. At the same time, transistor Q₃ is turned ON, which will make the V_OUT2 to be LOW. It corresponds to the OR gate output.

Similarly, if both the input of transistors Q₁ and Q₂ are HIGH, it will turn on both the transistors. It will drive the output at terminal V_OUT1 to be LOW. The transistor Q₃ is turned OFF during this operation. It will drive the output at terminal V_OUT2 to be HIGH.

The truth table for OR/NOR gate is shown below.

Advantages

• High-speed operation is possible and so the fastest logic family.
• Since transistors are not allowed to enter into saturation, which reduces the storage delay.
• Fan-out capability is high.

Apart from the advantages, it also has its own disadvantage. For the fast switching of transistors, the low and high logic levels are kept close. It reduces the noise margin. Since transistors are not allowed to enter into saturation, the power consumption is more.